Extending an FET layout verification system to bipolar technology

Author

Gannett, Joel W.

Author_Institution

Bellcore, Morristown, NJ, USA

fYear

1988

fDate

12-13 Sep 1988

Firstpage

183

Lastpage

186

Abstract

Rink, an automatic layout verification system intended for FET technologies, has been enhanced to handle bipolar designs. A straightforward procedure that uses Rink´s parasitic capacitance extractor to solve the bipolar device identification problem is described. The bipolar enhancements to Rink have been used successfully on a set of seven high-speed bipolar chips designed for lightwave communication. These chips ranged in complexity from 23 to 67 devices. Full-custom, nonmanhattan layouts for these chips were created on polygon-pusher style layout editors. For each chip, Rink executed an automatic comparison of the netlist extracted from the layout against a SPICE reference netlist. The latter has been coded for SPICE design simulations. Several fatal connectivity errors were uncovered as were a few significant disparities in resistor values and transistor sizes

Keywords

bipolar integrated circuits; circuit layout CAD; Rink; SPICE design simulations; automatic layout verification; bipolar device identification; bipolar technology; connectivity errors; high-speed bipolar chips; lightwave communication; nonmanhattan layouts; parasitic capacitance extractor; polygon-pusher style layout editors; resistor values; transistor sizes; Bipolar transistors; Data mining; Design automation; FETs; Geometry; Graphics; Integrated circuit technology; Layout; Object recognition; Parasitic capacitance;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1988., Proceedings of the 1988

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1988.51074

Filename

51074