DocumentCode
2217934
Title
Simulation models of ESD event in ICs
Author
Lei, Jiang ; Xing, Yang ; Jiaji, Wang
Author_Institution
Mater. Sci. & Eng. Dept., Fudan Univ., Shanghai, China
Volume
2
fYear
2001
fDate
22-25 Oct. 2001
Firstpage
990
Abstract
ESD protection becomes more and more prevalent with the development of deep sub-micron technology. ESD simulation with right models can reduce the design and test cycle of ESD protection circuit, and optimize for ESD robustness as well as device performance. Several simulation models and practical examples are described to show the application of ESD simulation in this article. Integrated models that combine process, circuit and device simulation are the trends of development.
Keywords
VLSI; circuit simulation; electrostatic discharge; integrated circuit modelling; protection; ESD event; ESD protection; IC simulation; deep sub-micron technology; design cycle; device performance; device simulation; robustness; simulation models; test cycle; Circuit simulation; Circuit testing; Computational modeling; Discrete event simulation; Electrostatic discharge; Equations; Materials science and technology; Protection; Stress; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on
Print_ISBN
0-7803-6520-8
Type
conf
DOI
10.1109/ICSICT.2001.982062
Filename
982062
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