DocumentCode
2218174
Title
Towards one chip HDTV MPEG2 encoder LSI
Author
Jiang, Li ; Li, Dongju ; Haba, Shintaro ; Chawalit ; Kunieda, Hiroaki
Author_Institution
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
fYear
1998
fDate
11-14 May 1998
Firstpage
173
Lastpage
176
Abstract
In this paper, a dedicated hardware design for motion estimation LSI of MPEG2 is presented. Combining our bits truncation adaptive pyramid (BTAP) algorithm with window MSPA architecture, the hardware cost is reduced without much PSNR performance degradation. The core of the test chip working at 83 MHz performs a search range of ±67 for image size of 1920×1152 and achieves video rate of 60 field/s. It can be used for HDTV purposes. The chip size is 4.8 mm×4.8 mm with 0.5 μm 2-level metal CMOS technology
Keywords
CMOS digital integrated circuits; adaptive signal processing; high definition television; large scale integration; motion estimation; video coding; 0.5 micron; 83 MHz; CMOS technology; HDTV; MPEG2 encoder LSI; bits truncation adaptive pyramid algorithm; dedicated hardware design; image size; motion estimation LSI; video rate; window MSPA architecture; CMOS technology; Costs; Degradation; HDTV; Hardware; Large scale integration; Motion estimation; PSNR; Performance evaluation; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-4292-5
Type
conf
DOI
10.1109/CICC.1998.694930
Filename
694930
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