Title :
Test structures based VLSIC yield ramp maximization
Author :
Strojwas, Andrzej J. ; Ciplickas, Dennis ; Lee, Sherry
Abstract :
This paper addresses a new approach to yield learning of lead products in the most advanced technologies. We start by presenting the classification and evolution of yield loss mechanisms in the most recent and upcoming technology generations. Then we show a spectrum of yield loss characterization methods, from in-line to E-test to product test analysis. The main part of the paper is devoted to the presentation of specially designed test structures for the diagnosis of the dominant yield loss components such as random defects, and systematic and parametric effects.
Keywords :
VLSI; electron beam testing; failure analysis; integrated circuit modelling; integrated circuit testing; integrated circuit yield; production testing; E-test; VLSI yield ramp maximization; characterization vehicle methodology; failure analysis techniques; in-line testing; lead products; parametric effects; product test analysis; random defects; systematic effects; test structures; yield loss characterization methods; yield loss mechanisms; Circuit testing; Electronics industry; Fluctuations; Integrated circuit technology; Integrated circuit yield; Product design; Robustness; System testing; Vehicles; Very large scale integration;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on
Print_ISBN :
0-7803-6520-8
DOI :
10.1109/ICSICT.2001.982070
