Circuit impact of device and interconnect parasitics in a complementary low-voltage organic thin-film technology

A simulation case study to indicate advancement opportunities for a low-voltage complementary organic thin-film transistor (OTFT) technology is presented. A 3-bit unary current-steering digital-to-analog converter (DAC) is used as circuit test vehicle. The study is based on accurate agreement of simulated and measured data, owing to optimized DC/AC SPICE models for both p- and n-type OTFTs. The model is validated by transient measurements of the driving complementary logic thermometer decoder up to a maximum operating frequency of 1 kHz. The case study shows that an improved circuit performance will result from a smaller source and drain overlap with the gate electrode particularly in the n-type OTFT, from avoiding metal interconnect crossings, and from increasing the channel carrier mobility of the n-type OTFT.