Title :
Chip and package co-design technique for clock networks
Author :
Zhu, Qing ; Dai, Wayne W M
Author_Institution :
Microprocessor Technol., Intel Corp., Santa Clara, CA, USA
Abstract :
This paper presents the motivation and a case study for a new clock distribution technique: route the global clock on package. This technique can be used in single chips and multichip modules based on area I/Os of the flip chip technology. Due to 2-4 order lower interconnect resistance on package layers, the clock skew and path delay of the clock network are significantly reduced
Keywords :
clocks; delays; flip-chip devices; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; multichip modules; network routing; area I/Os; chip/package co-design; clock distribution technique; clock networks; clock skew; flip chip technology; global clock routing; interconnect resistance; multichip modules; path delay; Capacitance; Clocks; Delay; Dielectrics; Distributed computing; Inductance; Microprocessors; Multichip modules; Packaging; Wire;
Conference_Titel :
Multi-Chip Module Conference, 1996. MCMC-96, Proceedings., 1996 IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
0-8186-7286-2
DOI :
10.1109/MCMC.1996.510788
