DocumentCode
2218719
Title
An MCM/IC timing-driven placement algorithm featuring explicit design space exploration
Author
Esbensen, Henrik ; Euh, E.S.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1996
fDate
6-7 Feb 1996
Firstpage
170
Lastpage
175
Abstract
A genetic algorithm for building-block placement of MCMs and ICs is presented which simultaneously minimizes layout area and an Elmore-based estimate of the maximum path delay while trying to meet a target aspect ratio. Explicit design space exploration is performed by using a vector-valued, S-dimensional cost function and searching for a set of distinct solutions representing the best tradeoffs of the cost dimensions. Designers can then choose from the output set of feasible solutions. In contrast to existing approaches such as simulated annealing, neither weights nor bounds are needed, thereby eliminating the inherent practical problems of specifying these quantities. Promising results are obtained for various placement problems, including a real-world MCM design
Keywords
circuit layout CAD; circuit optimisation; delays; genetic algorithms; integrated circuit design; multichip modules; timing; Elmore-based estimate; MCM/IC timing-driven placement; building-block placement; explicit design space exploration; feasible solutions; genetic algorithm; layout area; maximum path delay; real-world MCM design; target aspect ratio; vector-valued S-dimensional cost function; Algorithm design and analysis; Circuit simulation; Constraint optimization; Cost function; Delay estimation; Genetic algorithms; Integrated circuit modeling; Multichip modules; Simulated annealing; Space exploration;
fLanguage
English
Publisher
ieee
Conference_Titel
Multi-Chip Module Conference, 1996. MCMC-96, Proceedings., 1996 IEEE
Conference_Location
Santa Cruz, CA
Print_ISBN
0-8186-7286-2
Type
conf
DOI
10.1109/MCMC.1996.510790
Filename
510790
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