Title :
Design of 10 GHz, 2.6 mW frequency divider in 0.25 μm CMOS
Author :
He, Chengiming ; Sun, Yi-He
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
This paper describes the design of high speed, low power-dissipation frequency divider. The circuit has wide applications in high-speed communication systems, especially in clock recovery and frequency synthesis. Since frequency divider is one of the key parts in the frequency synthesis, divider´s speed limits the precision and the frequency of the frequency synthesis. In the paper, a frequency divider configured as master-slave flip-flop based on RAM cell is presented. Using TSMC 0.25um CMOS SPICE parameters, the divider circuit is simulated with HSPICE and get such results: while operating at 10 GHz with the 2V supply voltage, it dissipates only 2.6mW.
Keywords :
CMOS integrated circuits; SPICE; flip-flops; frequency dividers; high-speed integrated circuits; integrated circuit design; low-power electronics; random-access storage; 0.25 micron; 10 GHz; 2 V; 2.6 mW; CMOS IC design; HSPICE simulation; RAM cell; clock recovery; communication system; frequency synthesis; high-speed low-power frequency divider; master-slave flip-flop; CMOS technology; Circuit simulation; Circuit synthesis; Clocks; Frequency conversion; Frequency synthesizers; Latches; Parasitic capacitance; Power dissipation; Voltage;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on
Print_ISBN :
0-7803-6520-8
DOI :
10.1109/ICSICT.2001.982099
