System on silicon, Where are we?

Since the early 70´s, chip complexity has been continuously growing at a rate that has never slowed down, targeting the gigabit complexities for DRAM around the year 2000. The consequences of such an evolution in the year 1996, is the capability to put several hundred kilobytes of memory on a single microprocessor core with complexities ranging in the 30 million transistors per chip. What is behind such an evolution is clearly two challenges that still have not been met: (a) Designing for such complexities, using system level design methodologies going from the behavioral level down to silicon (that means, software-hardware co-design, advanced floor planning and complex validation approaches). (b) Power conscious design (that means designing with data throughput constraints within the chip and minimizing power consumption with low-voltage, high-speed optimization of the device behavior). Capitalizing on intellectual property in a company will also be of major importance to address the new, emerging markets like multimedia, where experiences from various market segments should be reused in a single system on a chip. The reusability of functions previously designed in heterogeneous technologies will be needed (abstraction from netlist). The economy of system on chip remains to be proven in most of the applications where limited quantities are needed and where programmability may be the only solution to go to