Title :
A novel 10-transistor low-power high-speed full adder cell
Author :
Junming, Lu ; Yan, Shu ; Zhenghui, Lin ; Ling, Wang
Author_Institution :
VLSI Res. Inst., Shanghai Jiao Tong Univ., China
Abstract :
A novel high-speed low-power 10-transistor 1-bit full-adder cell is proposed in this paper. The critical path consists of an inverter, an XOR or XNOR gate and one pass transistor. The cell offers higher speed, lower power consumption and lower area than the standard implementations of the 1-bit full-adder cell. A prototype of the proposed adder cell in 0.35um technology has a delay time of 0.2417ns. It also exhibits low average dissipation of 4.936*10-5 watt at frequency of 100MHz. Simulation results have shown better performance over the standard implementations.
Keywords :
adders; high-speed integrated circuits; low-power electronics; 0.2417 ns; 0.35 micron; 1 bit; 100 MHz; 4.936×10-5 W; XNOR gate; XOR gate; inverter; low-power high-speed full adder cell; one-pass transistor; Adders; Circuits; Delay; Digital signal processing; Energy consumption; Equations; Inverters; Power dissipation; Power supplies; Very large scale integration;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on
Print_ISBN :
0-7803-6520-8
DOI :
10.1109/ICSICT.2001.982104
