Title :
Segment delay faults: a new fault model
Author :
Heragu, Keerthi ; Patel, Janak H. ; Agrawal, Vishwani D.
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
fDate :
28 Apr-1 May 1996
Abstract :
We propose a segment delay fault model to represent any general delay defect ranging from a spot defect to a distributed defect. The segment length, L, is a parameter that can be chosen based on available statistics about the types of manufacturing defects. Once L is chosen, the fault list contains all segments of length L and paths whose entire lengths are less than L. Both rising and falling transitions at the origin of segments are considered. Choosing segments of a small length can prevent an explosion of the number of faults considered. At the same time, a defect over a segment may be large enough to affect any path passing through it. We present an efficient algorithm to compute the number of segments of any possible length in a circuit. We define various classes of segment delay fault tests-robust, transition, and non-robust-that offer a trade-off between fault coverage and quality
Keywords :
VLSI; automatic testing; circuit analysis computing; delays; fault diagnosis; integrated circuit modelling; integrated circuit testing; logic testing; production testing; delay defect; distributed defect; falling transitions; fault model; manufacturing defects; nonrobust tests; rising transitions; robust tests; segment delay faults; spot defect; transition tests; Circuit faults; Circuit testing; Contracts; Delay effects; Distributed computing; Electrical fault detection; Fault detection; Helium; Propagation delay; Robustness;
Conference_Titel :
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7304-4
DOI :
10.1109/VTEST.1996.510832