Title :
Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design
Author :
Vázquez, Diego ; Huertas, José L. ; Rueda, Adoración
Author_Institution :
Centro Nacional de Microelectron., Seville Univ., Spain
fDate :
28 Apr-1 May 1996
Abstract :
This paper focuses on the implementation of the `sw-op amp´ concept for analog circuits testing. Some alternative CMOS implementations are presented and compared in terms of influential parameters from a performance and cost point of view. Results show that the impact on the performance, power dissipation, and cost in terms of area and design efforts provoked by the use of sw-opamp structures, can be significantly reduced through efficient design of this cell
Keywords :
CMOS analogue integrated circuits; analogue integrated circuits; design for testability; integrated circuit design; integrated circuit testing; operational amplifiers; CMOS implementations; DFT; IC testing; analog integrated circuits; area; cell design; design efforts; power dissipation; sw-op amp design; Analog circuits; Analog integrated circuits; Circuit testing; Costs; Design for testability; Integrated circuit testing; Mixed analog digital integrated circuits; Power dissipation; Process design; Shift registers;
Conference_Titel :
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7304-4
DOI :
10.1109/VTEST.1996.510833
