Title :
Flexible core generation for neural signal processing
Author :
Diepenhorst, M. ; Haseborg, H. Ter ; Venema, R.S. ; Nijhuis, J.A.G. ; Spaanenburg, L.
Author_Institution :
Dept. of Comput. Sci., Groningen Univ., Netherlands
Abstract :
The architecture and design of a CMOS core module for neural signal processing is presented. A logarithmic number representation is exploited to allow for multiplication with adaptive accuracy. This creates the facility to exchange accuracy for speed, both for the single instruction execution as during the parallelisation of a number of instructions. The core module is generated from a process independent silicon assembler. Details are given on a specific pipelined sign-magnitude implementation
Keywords :
digital signal processing chips; modules; neural chips; neural net architecture; pipeline arithmetic; CMOS core module; DIGILOG arithmetics; architecture; flexible core generation; logarithmic number representation; multiplication module; neural signal processing; pipelined processing; silicon assembler; Biological neural networks; Computer architecture; Concurrent computing; Digital signal processing; Hardware; Neural networks; Neurons; Parallel processing; Signal generators; Signal processing;
Conference_Titel :
Neural Networks Proceedings, 1998. IEEE World Congress on Computational Intelligence. The 1998 IEEE International Joint Conference on
Conference_Location :
Anchorage, AK
Print_ISBN :
0-7803-4859-1
DOI :
10.1109/IJCNN.1998.682347
