Title :
Improved backwards analysis for architectural vulnerability factor estimation
Author :
Hartl, Robert ; Rohatschek, Andreas J. ; Stechele, Walter ; Herkersdorf, Andreas
Author_Institution :
Corp. Res. Sector, Robert Bosch GmbH, Stuttgart, Germany
Abstract :
The effects of single event upsets (SEU) are becoming increasingly important to circuit designers. Exact and detailed error rate estimations are needed to determine a system´s level of reliability. The architectural vulnerability factor (AVF) is a measure for the relative reliability of a circuit. In this paper we outline the properties of several known approaches such as statistical testing (fault injection), probabilistic error propagation and formal techniques. In addition we present necessary improvements to the Backwards Analysis method for AVF estimation. These improvements allow the analysis of any kind of RT-level circuit. Finally we present optimizations of the algorithm, which result in linear runtime overhead for the analysis of circuits compared to their simulation time.
Keywords :
error statistics; integrated circuit design; integrated circuit reliability; integrated circuit testing; network analysis; optimisation; statistical testing; AVF estimation; RT-level circuit; SEU; architectural vulnerability factor estimation; circuit analysis; circuit designers; error rate estimations; formal techniques; improved backwards analysis; optimizations; probabilistic error propagation; relative circuit reliability; semiconductor devices; statistical testing; Analytical models; Barium; Circuit faults; Integrated circuit modeling; Logic gates; Registers; Timing;
Conference_Titel :
Semiconductor Conference Dresden (SCD), 2011
Conference_Location :
Dresden
Print_ISBN :
978-1-4577-0431-4
DOI :
10.1109/SCD.2011.6068756