Improvement of SRAM-based failure analysis using calibrated Iddq testing

This work presents a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap dictionary. We investigate the accuracy of the defect classification under different forms of voltage testing and current testing. In particular we investigate the benefit of using multiple Iddq current levels calibrated to remove normal parametric variations. We also investigate the effects of unmodeled defects and the ability to identify cases off certain and uncertain diagnosis. We have experimentally validated our approach using a production microprocessor cache