Title :
The best-case power-delay products for polysilicon-contacted bipolar-transistor gates. A theoretical study
Author :
Yung, S.-Y. ; Burk, D.E.
Author_Institution :
AT&T Lab., Reading, PA, USA
Abstract :
The best-case power-delay products for bipolar-transistor gates that have optimally designed transistors with polysilicon-contacted emitters, both with and without interfacial layers between the polysilicon and underlying emitter, are predicted. It is shown that gates that have one or the other of these contacted-resistors have comparable power-delay products. Because this modeling is very general, it is believed the results are applicable for arsenic as well as phosphorous-doped polysilicon-contacted bipolar transistors
Keywords :
bipolar transistors; elemental semiconductors; semiconductor device models; silicon; Si:As; Si:P; best-case power-delay products; interfacial layers; modeling; optimally designed transistors; polysilicon-contacted bipolar-transistor gates; Bipolar transistors; Charge carrier processes; Contact resistance; Delay; Doping; Electrons; Numerical simulation; Spontaneous emission; Surface resistance; Thermionic emission;
Conference_Titel :
Bipolar Circuits and Technology Meeting, 1988., Proceedings of the 1988
Conference_Location :
Minneapolis, MN
DOI :
10.1109/BIPOL.1988.51085
