An asynchronous totally self-checking two-rail code error indicator

In this paper an asynchronous TSC two-rail code error indicator is presented. Such an error indicator memorises error indications {00,11} generated by TSC checkers with time duration greater than a tolerant limit T and can be used to detect not only faults that cause logical errors bat also faults that cause additional delays. Thus, concurrent detection, of delay faults inside the checkers is an additional application of the proposed circuit. The proposed TSC error indicator is more efficient than the TSC error indicator presented by Gaitanis (see IEEE Trans. Comput., vol. 34, no. 8, p. 753-61, 1985) which, to the authors´ knowledge, is the only existing TSC error indicator in the open literature