DocumentCode :
2219605
Title :
Self-dual parity checking-A new method for on-line testing
Author :
Saposhnikov, Vl.V. ; Dmitriev, Alexandre ; Goessel, M. ; Saposhnikov, V.V.
Author_Institution :
St. Petersburg State Univ.
fYear :
1996
fDate :
28 Apr-1 May 1996
Firstpage :
162
Lastpage :
168
Abstract :
Self-dual parity checking as a modification of ordinary parity checking is proposed in this paper. This method is based on the newly introduced concept of a self-dual complement of a given Boolean function. The parity prediction function fp of ordinary parity checking is replaced by the self-dual complement δp of this function such that the module-2 sum of the outputs of the monitored circuit and of δp is an arbitrary self-dual Boolean function h. Because of the large number of possible choices for h as an arbitrary self-dual Boolean function, the area overhead for an optimal self-dual complement δp is small. Alternating inputs are applied to the circuit; the output h is alternating as long as no error occurs. The fault coverage of this method is almost the same as for parity checking. The usefulness of the proposed method is demonstrated for MCNC benchmark circuits
Keywords :
Boolean functions; VLSI; automatic testing; integrated circuit testing; integrated logic circuits; logic testing; Boolean function; error checking; fault coverage; online testing; self-dual complement; self-dual parity checking; Automatic testing; Boolean functions; Circuit faults; Combinational circuits; Cost function; Fault tolerance; Logic gates; Monitoring; Redundancy; Transportation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location :
Princeton, NJ
ISSN :
1093-0167
Print_ISBN :
0-8186-7304-4
Type :
conf
DOI :
10.1109/VTEST.1996.510852
Filename :
510852
Link To Document :
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