C36. Design and implementation CFAR processor with programmable timer

In this paper, we present configurable hardware architecture for adaptive processing of noisy signals for target detection based on CFAR algorithms. The architecture has been designed to deal with parallel/pipeline processing and to be configured for the CA-CFAR scheme. The paper also design and implement a processor synchronizer circuit to generate the required timing signals to the processor subsystems. The generation of these timing signals is done using microcontroller ATMGA16. This technique is based on dividing the pulse repetition time PRT into number of range cells. Microcontroller ATMGA 16 produces an output control signal for each range cell via its ports. This microcontroller can produce 24 individual control signals to the radar system. The implemented circuit generates saixteen radar control signals using port A and B through 256 range cells and show the superiority of the circuit for generating the radar control signals. The architecture has been implemented with a good performance improvement over software implementations. Results are presented and discussed.