D3. Design and simulation of novel single-electron coding nano-circuits using room temperature summing-inverter gates

Author

Yakout, Mohamed A. ; Rehan, Sameh E.

Author_Institution

Fac. of Eng., Mansoura Univ., Mansoura, Egypt

fYear

2012

fDate

10-12 April 2012

Firstpage

571

Lastpage

580

Abstract

The Single-Electron (SE) summing-inverter (SI) NOR and NAND gates are among the basic functional SE circuits. In this paper, the design of multi-input SE SI NOR and NAND gates are reviewed. Novel SE decimal-to-BCD encoders and SE binary decoders, which are composed of SI gates, are designed for all combinations of active inputs and outputs. The simulated designs work properly with only one voltage source of 500 mV for a wide range of temperatures (from 40K to 400K). The detailed schematic diagrams along with the corresponding SIMON 2.0 simulation results at room temperature (that include input and output signals as well as the stability diagrams) of the novel SE decimal-to-BCD encoders as well as the developed SE binary decoders are presented.

Keywords

binary codes; circuit stability; logic gates; nanoelectronics; single electron devices; summing circuits; SE binary decoder; SE circuit; SE decimal-to-BCD encoder; SIMON 2.0 simulation; multiinput SE SI NAND gate; multiinput SE SI NOR gate; room temperature summing-inverter gate; single-electron coding nanocircuit; single-electron summing-inverter; stability diagram; temperature 293 K to 298 K; temperature 40 K to 400 K; voltage 500 mV; Decoding; Educational institutions; Inverters; Logic gates; Silicon; Simulation; Stability analysis; NAND gate; NOR gate; binary-coded-decimal (BCD); decoder; encoder; room-temperature; single-electron (SE); single-electron transistor (SET); summing-inverter (SI);

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Science Conference (NRSC), 2012 29th National

Conference_Location

Cairo

Print_ISBN

978-1-4673-1884-6

Type

conf

DOI

10.1109/NRSC.2012.6208568

Filename

6208568