Faulty chip identification in a multi chip module system

A built-in self test scheme for multi chip module (MCM) systems based on data compression is presented which not only detects faults but also identifies the faulty chip. It is assumed that a faulty chip may generate many erroneous outputs. In this approach outputs from all the chips in the MCM are compressed into two bits using two linear space compressors and compared with two reference signals generated for a fault free system in a comparator. If they differ fault is detected and the faulty chip is identified using N consecutive outputs from the comparators, where N=log₂(M+1) and M denotes the number of chips in the MCM. The approach can be implemented in a field programmable gate array (FPGA) which can be part of an MCM. Multiple chip failures can be identified as long as the faults do not overlap during the N consecutive test patterns