DocumentCode
2220100
Title
Gate width optimization of PHEMT MMIC LNA for low power consumption
Author
Yuk, Jong Seol ; Choi, Byoung Gun ; Lee, You Sang ; Park, Chul Soon
Author_Institution
Sch. of Eng., Inf. & Commun. Univ., Taejon, South Korea
Volume
2
fYear
2001
fDate
22-25 Oct. 2001
Firstpage
1327
Abstract
We have developed C-band LNAs of a very low noise and of a very low power dissipation by using a commercially standard 0.25 μm T gate PHEMT technology. A 2-stage MMIC LNA of very low noise figure as low as 0.76 dB and gain of 16 dB at 5.4 GHz has been implemented using a minimum input matching network. Also an LNA of very low power consumption as small as 18 mW with 3 V power supply has been implemented using an optimization of gate width and circuit topology.
Keywords
HEMT integrated circuits; MMIC amplifiers; impedance matching; low-power electronics; 0.25 micron; 0.76 dB; 16 dB; 18 mW; 3 V; 5.4 GHz; C-band; MMIC; PHEMT MMIC LNA; T gate PHEMT technology; circuit topology; gate width; gate width optimization; low power consumption; minimum input matching network; power dissipation; Circuit topology; Energy consumption; Gain; Impedance matching; MMICs; Noise figure; PHEMTs; Power dissipation; Power supplies; Standards development;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on
Print_ISBN
0-7803-6520-8
Type
conf
DOI
10.1109/ICSICT.2001.982146
Filename
982146
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