Test response compaction using arithmetic functions

Configurations of registers and adders, subtracters, or arithmetic logic units, which are available in many data paths, can be utilized to generate test patterns and compact test responses. This paper analyzes aliasing in these configurations when the test responses of circuits with arbitrary combinational faults are compacted, and gives the limiting values that the aliasing probability tends to for increasing test lengths. Configurations that feed back the overflow during addition or the underflow during subtraction are the best choices. In some of them the probability of aliasing tends to a limiting value of 1/(2^k -1), which is almost the same as in compactors based on linear feedback shift registers with irreducible characteristic polynomials