Power consumption considerations of C-SET logics for digital applications

We have investigated the power consumption of a complementary capacitive coupled single electron transistor (complementary C-SET) inverter, based on conventional CMOS design methodology for digital applications using Monte Carlo simulations. Static dissipation due to thermally enhanced tunneling becomes significant as the operation temperature increases. It has been found that increment of output capacitance to suppress output voltage fluctuation causes a degradation in the switching speed, as well as an increase in power consumption. We also introduced a design scheme using multi-tunnel junction SET for reducing the power consumption of C-SET logic circuits. The C-SET inverter using a simple three-tunnel junction SET can reduce the leakage power dissipation by a factor of 10. Our results show that, while the power consumption per elementary C-SET logic gate can be made as small as 10^-9 W, high-density integration will not be obtained by using the same method with the CMOS circuit.