DocumentCode
2220431
Title
A physical design methodology for 1.3 GHz SPARC 64 microprocessor
Author
Ito, Noriyuki ; Komatsu, Hiroaki ; Tanamura, Yoshiyasu ; Yamashita, Ryoichi ; Sugiyama, Hiroyuki ; Sugiyama, Yaroku ; Hamamura, Hirofumi
Author_Institution
Fujitsu Ltd., Kawasaki, Japan
fYear
2003
fDate
13-15 Oct. 2003
Firstpage
204
Lastpage
210
Abstract
We present a physical design methodology that was applied to the design of Fujitsu 1.3 GHz SPARC 64 microprocessor. A tool-set called GigaGate was developed based on this methodology. The goal of GigaGate is to support the design team to complete the high-performance microprocessor design on schedule.
Keywords
application specific integrated circuits; circuit layout CAD; microprocessor chips; technology CAD (electronics); CAD technology; Fujitsu 1.3 GHz SPARC 64 microprocessor design; GigaGate tool; physical design methodology; Clocks; Delay estimation; Design automation; Design methodology; Design optimization; Logic; Microprocessors; Signal design; Timing; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 2003. Proceedings. 21st International Conference on
ISSN
1063-6404
Print_ISBN
0-7695-2025-1
Type
conf
DOI
10.1109/ICCD.2003.1240896
Filename
1240896
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