Title :
Consistently dominant fault model for tristate buffer nets
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
fDate :
28 Apr-1 May 1996
Abstract :
Unknown values result from floating and contention type faults on tristate buffer nets thereby causing MISR signature loss during test pattern compression. A Consistently Dominant Fault model is presented that removes the problem and permits fault detection of several problem tristate buffer stuck faults
Keywords :
VLSI; buffer circuits; fault diagnosis; fault location; integrated circuit testing; integrated logic circuits; logic testing; multivalued logic circuits; ternary logic; MISR signature loss; consistently dominant fault model; contention type faults; fault detection; floating type faults; stuck faults; test pattern compression; tristate buffer nets; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Fault diagnosis; Instruments; Monitoring; Pattern analysis; Polynomials;
Conference_Titel :
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7304-4
DOI :
10.1109/VTEST.1996.510885
