Title :
An unexpected factor in testing for CMOS opens: the die surface
Author :
Konuk, Haluk ; Ferguson, F. Joel
Author_Institution :
California Design Center, Hewlett-Packard Co., CA, USA
fDate :
28 Apr-1 May 1996
Abstract :
We present the experimental evidence, for the first time, that the die surface can act as an RC interconnect, becoming an important factor in determining the voltage of a floating wire created by a CMOS open. We present a circuit model for this effect verified with HSPICE simulations. A detailed analysis of potential mechanisms behind this phenomenon is provided. We also present our measurement results for the trapped charge deposited on floating gates during fabrication
Keywords :
CMOS integrated circuits; VLSI; electric charge; integrated circuit modelling; integrated circuit testing; surface phenomena; CMOS opens; HSPICE simulations; RC interconnect; circuit model; die surface; floating gates; trapped charge; Capacitance; Charge measurement; Current measurement; Fabrication; Integrated circuit interconnections; Packaging; Semiconductor device modeling; Testing; Voltage; Wire;
Conference_Titel :
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7304-4
DOI :
10.1109/VTEST.1996.510888
