Title :
High-speed HEC algorithm for ATM
Author :
Suh, Chung-Wook ; Kim, Kyung-Soo
Author_Institution :
Div. of Semicond. Technol., ETRI, Taejon, South Korea
Abstract :
A high-speed HEC (header error control) algorithm for the 16-bit mode of ATM (asynchronous transfer mode) interface system is presented. Thanks to using the property of the Galois field and the parallelism of the linear feedback shift register, this algorithm is very efficient and simple in accomplishing the more than 622 Mbps of cell transmission. Through implementing in VHDL (very-high-speed-integrated-circuit hardware description language), the comparison of the proposed algorithm with the byte-mode algorithm shows that the proposed algorithm has lower latency, higher throughput and less hardware complexity than the latter
Keywords :
Galois fields; asynchronous transfer mode; error correction codes; hardware description languages; network interfaces; shift registers; 16 bit; 16-bit mode; ATM interface system; Galois field; VHDL; asynchronous transfer mode; byte-mode algorithm; cell transmission; hardware complexity; header error control; high-speed HEC algorithm; latency; linear feedback shift register; throughput; very-high-speed IC hardware description language; Clocks; Delay; Error correction; Galois fields; Hardware design languages; Linear feedback shift registers; Payloads; Physical layer; Standardization; Throughput;
Conference_Titel :
Information, Communications and Signal Processing, 1997. ICICS., Proceedings of 1997 International Conference on
Print_ISBN :
0-7803-3676-3
DOI :
10.1109/ICICS.1997.652048
