Title :
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator
Author :
Amin, Minesh B. ; Vinnakota, Bapiraju
Author_Institution :
Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
fDate :
28 Apr-1 May 1996
Abstract :
Sequential circuit fault simulators use the multiple bits in a computer data word to accelerate simulation. We introduce, and implement, a new sequential circuit fault simulator, a parallel pattern parallel fault simulator, ZAMBEZI, which simultaneously simulates multiple faults with multiple vectors in one data word. ZAMBEZI is developed by enhancing the control flow, of existing parallel pattern algorithms. For a very wide range of benchmark circuits, compared to parallel fault and parallel pattern simulators, ZAMBEZI offers either the best, or very close to the best, uniprocessor performance. ZAMBEZI also offers superior performance when parallelized
Keywords :
VLSI; circuit analysis computing; fault diagnosis; integrated logic circuits; logic testing; parallel algorithms; sequential circuits; ZAMBEZI; multiple faults simulation; multiple vectors; parallel fault simulation; parallel pattern simulator; sequential circuit fault simulator; Acceleration; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer science; Computer simulation; Logic testing; Parallel processing; Sequential circuits;
Conference_Titel :
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7304-4
DOI :
10.1109/VTEST.1996.510890
