A mixed-mode delay-locked-loop architecture

Author

Eckerbert, Daniel ; Svensson, Lars J. ; Larsson-Edefors, Per

Author_Institution

Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden

fYear

2003

fDate

13-15 Oct. 2003

Firstpage

261

Lastpage

263

Abstract

We present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock generation. In contrast to analog DLLs, the proposed architecture allows for clock-gating; moreover, circuit simulations indicate that its performance (in terms of maximum frequency, frequency range, and low-speed power dissipation) is superior to that of a previously-reported, purely digital DLL.

Keywords

circuit simulation; delay lock loops; digital phase locked loops; mixed analogue-digital integrated circuits; phase detectors; power consumption; analog DLL; circuit simulation; clock-gating; digital DLL; mixed-mode delay-locked-loop architecture; multiple-phase clock generation; phase detectors; power consumption; Chromium; Circuits; Clocks; Computer architecture; Delay; Digital control; Filters; Frequency; Gold; Weight control;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2003. Proceedings. 21st International Conference on

ISSN

1063-6404

Print_ISBN

0-7695-2025-1

Type

conf

DOI

10.1109/ICCD.2003.1240904

Filename

1240904

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2220622