Title :
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits
Author :
Lee, Terry ; Hajj, Ibrahim N. ; Rudnick, Elizabeth M. ; Pate, Janak H.
Author_Institution :
Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
fDate :
28 Apr-1 May 1996
Abstract :
An efficient automatic test pattern generator for IDDQ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. An adaptive genetic algorithm (GA) is used to generate compact test sets. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented. The results show that GA-based test generators are very well suited for generating compact test sets for IDDQ testing of bridging faults
Keywords :
CMOS digital integrated circuits; VLSI; automatic testing; fault location; genetic algorithms; integrated circuit testing; logic testing; ATPG; CMOS VLSI circuits; CMOS digital circuits; GA-based test generators; IDDQ current testing; adaptive genetic algorithm; automatic test pattern generator; bridging faults; compact test set generation; two-line bridging fault set; Automatic test pattern generation; Automatic testing; CMOS digital integrated circuits; Circuit faults; Circuit testing; Laboratories; Sequential circuits; System testing; Test pattern generators; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7304-4
DOI :
10.1109/VTEST.1996.510893
