DocumentCode :
2220684
Title :
A novel test generation approach for parametric faults in linear analog circuits
Author :
Zheng, Hong Helena ; Balivada, Ashok ; Abraham, Jacob A.
Author_Institution :
Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
fYear :
1996
fDate :
28 Apr-1 May 1996
Firstpage :
470
Lastpage :
475
Abstract :
While analog test generation tools are still in their infancy, the corresponding tools in the digital domain have reached a fair degree of maturity and acceptance. Recognizing this fact, we propose a novel test generation method for linear analog circuits that employs well established digital test software to generate time-domain tests for analog parametric faults. We transform the analog circuit to an equivalent digital circuit, and target only those stuck-at faults in the digital circuit that could possibly capture parametric failures in the original analog circuit. Hence, the sequence of digital test vectors obtained from any test generator represents a test waveform for the analog parametric faults. The technique is illustrated using examples that show this to be a simple, yet attractive alternative to costlier simulation-based analog test generation approaches
Keywords :
VLSI; analogue integrated circuits; analogue processing circuits; equivalent circuits; fault location; integrated circuit testing; time-domain analysis; digital test software; digital test vectors; equivalent digital circuit; linear analog circuits; parametric faults; stuck-at faults; test generation; test waveform; time-domain tests; AC generators; Analog circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Digital circuits; Electrical fault detection; Jacobian matrices; Software testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1996., Proceedings of 14th
Conference_Location :
Princeton, NJ
ISSN :
1093-0167
Print_ISBN :
0-8186-7304-4
Type :
conf
DOI :
10.1109/VTEST.1996.510895
Filename :
510895
Link To Document :
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