DocumentCode
2220881
Title
Test data compression and compaction for embedded test of nanometer technology designs
Author
Rajski, Janusz ; Tyszer, Jerzy
Author_Institution
Mentor Graphics Corp., Wilsonville, OR, USA
fYear
2003
fDate
13-15 Oct. 2003
Firstpage
331
Lastpage
336
Abstract
We examine various forms of embedded deterministic test with particular emphasis on input stimuli compression and test response compaction schemes. Subsequently, the embedded deterministic test (EOT) scheme, which significantly reduces manufacturing test cost by providing a dramatic reduction in scan test data volume and scan test time, is discussed.
Keywords
automatic test pattern generation; boundary scan testing; data compression; design for testability; embedded systems; fault diagnosis; embedded deterministic test; manufacturing test cost; nanometer technology designs; scan test data volume; scan test time; test data compression; test response compaction schemes; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Compaction; Copper; Costs; Design for testability; Test data compression; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 2003. Proceedings. 21st International Conference on
ISSN
1063-6404
Print_ISBN
0-7695-2025-1
Type
conf
DOI
10.1109/ICCD.2003.1240915
Filename
1240915
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