• DocumentCode
    2221621
  • Title

    On simulating faults in parallel

  • Author

    Iyengar, V.S. ; Tang, D.T.

  • Author_Institution
    IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • fYear
    1988
  • fDate
    27-30 June 1988
  • Firstpage
    110
  • Lastpage
    115
  • Abstract
    Hardware engines (e.g. YSE and EVE) have been built to perform functional simulation of large designs over many patterns. The authors present a method of simulating faults in parallel that is applicable to these hardware simulation engines (and to software simulators with similar characteristics). A notion of independence between faults is used to determine the faults that can be simulated in parallel. An efficient algorithm is developed to determine the independent subsets of faults. Results of applying the algorithm to large examples are presented and shown to be very good by comparing them with theoretical lower bounds. This technique makes it feasible to fault simulate large networks using these hardware simulation engines.<>
  • Keywords
    digital simulation; fault tolerant computing; parallel architectures; virtual machines; fault simulation; functional simulation; hardware simulation engines; parallel simulation; Computational modeling; Computer architecture; Discrete event simulation; Engines; Hardware; Logic design; Logic gates; Logic testing; Pins; Sequential analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Fault-Tolerant Computing, 1988. FTCS-18, Digest of Papers., Eighteenth International Symposium on
  • Conference_Location
    Tokyo, Japan
  • Print_ISBN
    0-8186-0867-6
  • Type

    conf

  • DOI
    10.1109/FTCS.1988.5307
  • Filename
    5307