Low-density parity-check decoder architecture for high throughput optical fiber channels

Author

Selvarathinam, Anand ; Kim, Euncheol ; Choi, Gwan

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

2003

fDate

13-15 Oct. 2003

Firstpage

520

Lastpage

525

Abstract

A requirement-specific decoder design for forward error-correction in 2 Gbps optical fiber communication system is presented. Low-density parity-check codes are used to achieve high bit error rate performance. Several novel error-decoding architectures are proposed and their design configurations explored to identify optimal cost/performance design. Serial, parallel and scalable architectures are studied. The result is a scaleable architecture that consists of 1.3 million CMOS gates running at 295 MHz and it achieves a throughput of 2.51 Gbps.

Keywords

VLSI; error statistics; forward error correction; optical fibre networks; parity check codes; CMOS gate; LDPC decoder; VLSI; error-decoding architecture; forward error-correction; hardware scaling; low-density parity-check decoder architecture; optical fiber channel; optimal cost; parallel architecture; scalable architecture; serial architecture; Bit error rate; Computer architecture; Decoding; Forward error correction; Hardware; Optical fiber communication; Optical fiber devices; Optical fibers; Parity check codes; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2003. Proceedings. 21st International Conference on

ISSN

1063-6404

Print_ISBN

0-7695-2025-1

Type

conf

DOI

10.1109/ICCD.2003.1240949

Filename

1240949