Title :
Reducing operand transport complexity of superscalar processors using distributed register files
Author :
Bunchua, Santithorn ; Wills, D. Scott ; Wills, Linda M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. Here, a distributed register file architecture that employs fully distributed functional unit clusters is presented. It utilizes a local register mapping table and a dedicated register transfer network to support distributed register operations. In addition, an eager transfer mechanism is developed to reduce penalties caused by incomplete operand transport interconnection. Distributed register files can be employed to reduce operand access time by a factor of two with associated average IPC penalties of 14% and 21% on 4- and 8-way superscalar architectures across a broad range of symbolic, scientific, and multimedia applications. The IPC penalties are only 3% and 10% for SpecINT2000 applications.
Keywords :
communication complexity; distributed databases; multiprocessing systems; central register file; distributed functional unit clusters; distributed register file; local register mapping table; operand bypass network; operand transport complexity; register transfer network; superscalar processor; Clocks; Computer architecture; Computer networks; Delay effects; Distributed computing; Frequency; Registers; Time factors; VLIW; Wire;
Conference_Titel :
Computer Design, 2003. Proceedings. 21st International Conference on
Print_ISBN :
0-7695-2025-1
DOI :
10.1109/ICCD.2003.1240951