A system LSI utilizing media processor core “MMA”

Author

Kamijo, S. ; Wakimoto, Y. ; Satoh, T. ; Sakurai, A. ; Gotoh, E. ; Nakajima, M.

Author_Institution

Fujitsu Labs. Ltd., Kawasaki, Japan

fYear

1998

fDate

11-14 May 1998

Firstpage

181

Lastpage

184

Abstract

We have developed a system LSI utilizing media processor core “MMA”. The LSI will be ready to deliver to general customers from Jan. 1998. The MMA is a processor core which offers 1BOPS of performance at 180 MHz to realize MPEG2 real time decoding. The MMA size is 3.3 mm*3.1 mm in the implementation utilizing 3 ML 0.35 um technology. This is handy enough to integrate with various function blocks, such as GDC, bus bridges to form a system LSI dedicated for real time multi-media operations. The LSI runs at 100 MHz accompanying SPARClite RISC CPU. For the concurrent operations between the LSI and SPARClite, a dedicated task queuing scheme has been defined to maximize the sustained performance. In this paper, we describe the architecture of the LSI, and discuss our performance evaluation result of MPEG decoding utilizing this task queuing scheme

Keywords

decoding; digital signal processing chips; large scale integration; multimedia computing; real-time systems; reduced instruction set computing; video signal processing; 0.35 micron; 180 MHz; GDC; MMA media processor core; MPEG2 real time decoding; SPARClite RISC CPU; bus bridges; concurrent operations; dedicated task queuing scheme; real time multi-media operations; system LSI; Application software; Bridges; Computer architecture; Control systems; Decoding; Large scale integration; Modems; Multimedia systems; Pipelines; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.694958

Filename

694958