A low power, high performance, 960 macrocell, SRAM based complex PLD

Author

Shimanek, Schuyler ; Maldonado, Cesar ; Ruybalid, Victor ; Darling, Roy

Author_Institution

Philips Semicond., Albuquerque, NM, USA

fYear

1998

fDate

11-14 May 1998

Firstpage

255

Lastpage

260

Abstract

The design, process features and performance of a 960 macrocell, low power, high density complex programmable logic device (CPLD) is presented. It is fabricated on a 0.35 μm, five layer metal, CMOS process which permits this 8.5 million transistor design to fit on a 140 mm² die, dissipate only 330 μW of static power at a supply voltage of 3.3 V, and allow system operation of up to 225 MHz

Keywords

CMOS logic circuits; circuit CAD; design for testability; integrated circuit design; integrated circuit testing; logic CAD; logic testing; programmable logic arrays; programmable logic devices; 0.35 micron; 225 MHz; 3.3 V; 330 muW; DFT; PAL block; SRAM based complex PLD; complex programmable logic device; five layer metal CMOS process; high density CPLD; high performance device; low power operation; macrocell; Circuit testing; Frequency; Integrated circuit interconnections; Logic arrays; Logic design; Macrocell networks; Programmable logic arrays; Programmable logic devices; Random access memory; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.694975

Filename

694975