DocumentCode
2222588
Title
Implementing logic in FPGA embedded memory arrays: architectural implications
Author
Wilton, Steven J E
Author_Institution
Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
fYear
1998
fDate
11-14 May 1998
Firstpage
269
Lastpage
272
Abstract
It has become clear that embedded memory arrays will be essential in future FPGAs. These arrays were originally intended to implement storage, but recent work has shown that they can also be used to implement logic very efficiently. In this paper, we explore how the depth, width, and flexibility of the embedded arrays affect their ability to implement logic. It is shown that each array should contain between 512 and 2048 bits, and should have a word width that can be configured as 1, 2, 4, or 8
Keywords
field programmable gate arrays; logic design; memory architecture; read-only storage; 512 to 2048 bit; FPGA embedded memory arrays; ROM; architectural implications; array size; array width; Field programmable gate arrays; Lattices; Logic arrays; Logic circuits; Logic design; Random access memory; Read-write memory; Service oriented architecture; Space exploration; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-4292-5
Type
conf
DOI
10.1109/CICC.1998.694978
Filename
694978
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