• DocumentCode
    2222743
  • Title

    TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing

  • Author

    Spjut, Josef ; Boulos, Solomon ; Kopta, Daniel ; Brunvand, Erik ; Kellis, Spencer

  • Author_Institution
    Sch. of Comput., Univ. of Utah, Salt Lake City, UT
  • fYear
    2008
  • fDate
    8-9 June 2008
  • Firstpage
    108
  • Lastpage
    114
  • Abstract
    Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, multi-core processor architecture that performs real-time ray tracing. Our architecture, called TRaX for Threaded Ray eXecution, consists of a set of thread states that include commonly used functional units for each thread and share large functional units through a programmable interconnect to maximize utilization. The memory system takes advantage of the application´s read-only access to the scene database and write-only access to the frame buffer output to provide efficient data delivery with a relatively simple structure. Preliminary results indicate that a multi-core version of the architecture running at a modest speed of 500 MHz already provides real-time ray traced images for scenes of a complexity found in video games. We also explore the architectural impact of a ray tracer that uses procedural (computed) textures rather than image-based (look-up) textures to trade computation for reduced memory bandwidth.
  • Keywords
    multi-threading; ray tracing; real-time systems; TRaX; Threaded Ray eXecution; computer graphics image; data delivery; frequency 500 MHz; image-based texture; memory bandwidth; memory system; multicore processor architecture; multithreaded architecture; programmable interconnect; real-time ray tracing; Bandwidth; Computer architecture; Computer graphics; Games; Image databases; Layout; Multicore processing; Ray tracing; Read-write memory; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application Specific Processors, 2008. SASP 2008. Symposium on
  • Conference_Location
    Anaheim, CA
  • Print_ISBN
    978-1-4244-2333-0
  • Electronic_ISBN
    978-1-4244-2334-7
  • Type

    conf

  • DOI
    10.1109/SASP.2008.4570794
  • Filename
    4570794