A low-power, small-area 1 MSample/sec ADC for neural-signal recording systems in 0.35-µm CMOS

A fully differential, low-power, area-efficient analog to digital converter has been designed and simulated for implantable neural signal recording systems. Proposed ADC consisted of an analog stage, similar to a pipeline converter stages but reused it to extract the final effective bits. This paper presents a 9-bit 1-MSample/s analog to digital converter with stage reused technique that has been designed and simulated with standard 2P4M 0.35 mum CMOS process. High speed comparators, differential operational amplifier and digital correction are circuit techniques, have been used in the ADC. Simulation results comprehend a peak SNDR and ENOB of 54.3 dB and 8.7 bit; respectively with a full-scale 2 V sinusoidal input at 39.0625 kHz and a peak differential nonlinearity (DNL) of 0.45 relative to the least significant bit (LSB).The total power dissipation for a complete conversion cycle of 9 bit, is 430 muW from a 3 V supply.