Title :
Research on floorplanning
Author :
Cheng, Chung-Kuan
Author_Institution :
California Univ., San Diego, CA, USA
Abstract :
Summary form only given. We discuss our recent progress of block placement for floorplanning. We first extended zone refinement to cluster refinement. We then devised an O-tree floorplan representation for efficient and effective floorplan operations. Lately, we explored the relations between floorplan representations, i.e. slicing O-tree, sequence pairs, corner block list, O-tree, and twin binary trees
Keywords :
circuit layout; trees (mathematics); O-tree; block placement; cluster refinement; corner block list; floorplanning; sequence pair; slicing O-tree; twin binary trees; zone refinement; Analog circuits; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Design for testability; Failure analysis; Logic testing; System-on-a-chip;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982492
