Title :
Challenges on global routing correlation
Author :
Chiang, Charles ; Shenoy, Narendra
Author_Institution :
Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
Abstract :
We study global routing for correlation between placement and detailed routing. We propose some new approaches during global routing to help correlation. We discuss how using concepts of global cell size, three-dimensional global routing, multithread global routing can achieve better correlation without impacting the run time and memory
Keywords :
VLSI; circuit layout CAD; integrated circuit layout; network routing; IC layout; detailed routing; global cell size; global routing correlation; multithread global routing; placement; three-dimensional global routing; Degradation; Fabrication; Feedback; Foundries; Integrated circuit interconnections; Routing; Runtime; Time to market; Timing; USA Councils;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982495
