Title :
Greedy algorithm for register-transfer level ALU mapping
Author :
Zhou, Haifeng ; Lin, Zhenghui
Author_Institution :
LSI Res. Inst., Jiao Tong Univ., Shanghai, China
Abstract :
We present register-transfer level mapping (RTLM), a library mapping technique for RT level components that supports the current design methodologies using high-level design and design reuse. This technique is well suited for mapping regularly structured datapaths, i.e. ALUs. Experiments show that the RTLM is an effective approach for reuse of datapath components in high-level synthesis
Keywords :
application specific integrated circuits; circuit CAD; digital arithmetic; high level synthesis; integrated circuit design; ALUs; RT level components; RTLM; datapath component reuse; design methodologies; design reuse; greedy algorithm; high-level design; high-level synthesis; library mapping technique; register-transfer level ALU mapping; register-transfer level mapping; regularly structured datapath mapping; technology mapping; Arithmetic; Design methodology; Greedy algorithms; High level synthesis; Job design; Large scale integration; Logic design; Signal design; Signal synthesis; Software libraries;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982507
