Title :
Methods of improving rout ability in timing-driven placement
Author :
Wenting, Hou ; Xianlong, Hong ; Weimin, Wu ; Yici, Cai
Author_Institution :
Dept. of Comput. Sci., Tsinghua Univ., Beijing, China
Abstract :
How to decrease the maximum delay and how to improve the routability are two important goals in the placement algorithm, but there are some conflicts between the two goals. In this paper, we provide two heuristic methods to reach the two goals during the global placement stage. In both of the methods, the algorithms include two steps. We try to decrease the maximum delay in the first step, then in the next step we adjust the cell position in the local area to improve the routability. We have tested our two algorithms using two real circuits, and the results show that the maximum delay and the number of critical paths do not increase a lot, while the routability improved
Keywords :
VLSI; circuit layout CAD; integrated circuit layout; network routing; timing; critical paths; global placement stage; heuristic methods; local area cell position; maximum delay; routability; timing-driven placement; two step algorithms; very large-scale integrated circuits; Circuit synthesis; Circuit testing; Computer science; Delay; Integrated circuit interconnections; Routing; Timing; Very large scale integration; Wire; Wiring;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982510
