• DocumentCode
    2224391
  • Title

    A mixed mode placement algorithm for combined design of macro blocks and standard cells

  • Author

    Weimin, Wu ; Xianlong, Hong ; Yici, Cai ; Changqi, Yang ; Jun, Gu

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    122
  • Lastpage
    125
  • Abstract
    A hierarchical automatic placement algorithm for mixed mode placement problems is presented. The so-called mixed mode is a combination of standard cells and macro blocks. The presented algorithm completes the placement at both block level and cell level. In block level, the random cells are firstly partitioned into soft blocks, then a SP (sequence pair) based method (Murata et al, IEEE Trans. CAD, vol. 15, pp. 1518-1524, 1996) is used for block placement. In cell level, firstly, a quadratic placement method is used for inner placement within each soft block, then a placement improvement routine is done to the whole chip, and finally, a combined min-cut and enumeration based detailed placement procedure completes the final placement. The algorithm is tested on a set of circuits with different numbers of standard cells and macro blocks, and obtains satisfactory results
  • Keywords
    cellular arrays; circuit layout CAD; integrated circuit layout; integrated logic circuits; logic CAD; logic partitioning; network routing; block level placement; block level random cell partitioning; block placement; cell level placement; cell level quadratic placement method; combined design; combined min-cut/enumeration based placement procedure; final placement; hierarchical automatic placement algorithm; inner placement; macro blocks; mixed mode placement algorithm; mixed mode placement problem; mixed mode standard cell/macro block combination; placement improvement routine; sequence pair based method; soft blocks; standard cells; Algorithm design and analysis; Atherosclerosis; Circuit testing; Computer science; Hidden Markov models; Law; Partitioning algorithms; Read only memory; Shape; Simulated annealing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2001. Proceedings. 4th International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    0-7803-6677-8
  • Type

    conf

  • DOI
    10.1109/ICASIC.2001.982513
  • Filename
    982513