An Optimization Approach for QEMU

Binary translation system usually maps guest registers into host registers to accelerate the translation speed. QEMU can be treated as a typical binary translator and it uses a fixed register allocation. On most hosts, QEMU simply maps all the target registers to memory and only store a few temporary variables in host registers. However, QEMU does not consider the dependence of two or more adjacent instructions. So even a guest register´s value has been loaded into the temporary variables when executing the previous instruction, the next instruction could not use the value from the temporary variable directly, which is mapped into host register. The next instruction has to reload the value from memory again. This paper presents an approach to eliminate these unnecessary operations. Tests of benchmarks from nbench show that this approach can achieve 10%~20% speed improvement.