Folding pipeline architecture based on the least-energy algorithm for high level synthesis

Author

Sheng, Zhang ; Ning, Zhu ; Runde, Zhou ; Yuanqing, Ge

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2001

fDate

2001

Firstpage

159

Lastpage

162

Abstract

Pipeline architecture is very important in high level design and synthesis of digital circuits, especially for datapath design. The paper focuses on the folding pipeline architecture, presenting a new transform method for resources allocation with timing constraints. A least-energy folding and cycling schedule algorithm is proposed for synthesis, and a pipelined architecture based on a butterfly net is realized, which has benefits for interconnection design in deep-submicron technology

Keywords

circuit CAD; digital integrated circuits; high level synthesis; hypercube networks; integrated circuit design; integrated circuit interconnections; pipeline processing; processor scheduling; resource allocation; timing; butterfly net; datapath design; digital circuits; folding pipeline architecture; high level design; high level synthesis; interconnection design; least-energy algorithm; least-energy folding/cycling schedule algorithm; pipelined architecture; resources allocation; timing constraints; transform method; Algorithm design and analysis; Circuit synthesis; Clocks; Computer architecture; High level synthesis; Pipelines; Processor scheduling; Resource management; Scheduling algorithm; Springs;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982521

Filename

982521