A high-level tool for the development of FPLD-based stochastic neural networks

This paper presents a high level tool that assists in the creation of stochastic neural networks for implementation on field programmable logic devices (FPLDs). The tool includes an automatic neural network synthesiser and utilities for assisting in the analysis of the resulting design. The neural network synthesis tool takes a weight matrix description of a network´s neural interconnections and produces a complete hardware description that can be compiled for any particular device. The motivation for this research is to give an example of how the details of FPLDs can be hidden from a designer, allowing their configuration to be specified at a high level. It is important that the tool produces not only a solution, but that the method used in the solution both supports and exploits the use of programmable hardware