DocumentCode :
2224684
Title :
Effects of delay models on maximum power estimation of VLSI circuits
Author :
Junming, Lu ; Zhenghui, Lin
Author_Institution :
LSI Res. Inst., Shanghai Jiaotong Univ., China
fYear :
2001
fDate :
2001
Firstpage :
179
Lastpage :
182
Abstract :
Previous work has shown that maximum switching density at a given node is extremely sensitive to a slight change in the delay at that node. In this paper, five delay models have been discussed in terms of maximum power estimation of VLSI sequential circuits. The effects of these delay models are analyzed. Results for the five delay models are reported for ISCAS89 sequential benchmark circuits
Keywords :
VLSI; circuit simulation; covariance analysis; delays; genetic algorithms; integrated circuit modelling; logic simulation; parameter estimation; sequential circuits; ISCAS89 sequential benchmark circuits; VLSI circuits; VLSI sequential circuits; circuit node; delay models; genetic algorithm; maximum power estimation; maximum switching density; node delay; statistic delay model; Delay effects; Delay estimation; Genetic algorithms; Libraries; Power dissipation; Power measurement; Sequential circuits; Statistics; Switching circuits; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
Type :
conf
DOI :
10.1109/ICASIC.2001.982526
Filename :
982526
Link To Document :
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